Research Engineer - RTL OoO Core Development (RE2)

Job Description

• Research of computer architectural techniques and development of RTL hardware structures related to superscalar OoO core design to improve the efficiency, scalability, and performance of a current RISC-V core.


• Review and analyze the state-of-the-art performance techniques for OoO processor architectures to identify the most effective approaches.


• Design RTL structures by implementing the selected techniques for RISC-V CPU architectures.
  
  Implement complex control logic, data paths, and microarchitectural features in SystemVerilog.


• Integration into RISC-V Core: This integration should provide an efficient and configurable means of RISC-V processor cores with the new capabilities, demonstrating a tradeoff balance with performance improvements.


• Verification and Validation: Develop a verification strategy with CoCoTB for the derived modules and Python hardware modeling.
  
  Implement verification tests and validation procedures to ensure correctness and functionality.


• Performance Evaluation: Evaluate the impact of the new capabilities on the RISC-V processor core through extensive simulation and benchmarking.
  
  Measure the improvements in terms of execution efficiency, reduced cycle count, and overall performance.


• Follow the methodology and quality standards for the code base development.


• Documentation and Reporting: Document design specifications, microarchitecture, and test plans.
  
  Prepare reports and presentations on design progress, issues, and performance metrics.


• Tool and Methodology Development: Develop and maintain scripts and tools to automate design and verification tasks.
  
  Contribute to the improvement of design and verification methodologies within the team.


• Code Quality and Maintenance: Ensure high-quality, maintainable, and reusable RTL code.
  
  Perform code reviews and provide constructive feedback to peers.


• Compliance and Standards: Ensure design compliance with industry standards and best practices.
  
  Follow project-specific guidelines and contribute to the establishment of new standards within the team.

• 
  Education
  
  
  
  • BS or MS in Telecommunication, Electronics, Computer Science, or Computer Engineering.
  
  
  
  


• 
  Essential Knowledge and Professional Experience
  
  
  
  • Logic Circuit Design Knowledge.
  
  
  • Proficiency in SystemVerilog.
  
  
  • Computer architecture Knowledge.
  
  
  • Familiarity with RISC-V Specification
  
  
  • Git version control system Knowledge.
  
  
  • Python and CoCoTB.
  
  
  • Proficiency with standard open-source and industry tools for RTL simulation.
    
    
    
    Computer architecture Knowledge.
  
  
  • Direct Programming Interface for HW Modeling and Host Interfacing.
    
    
  
  
  • Make, Bash, Docker
  
  
  
  


• 
  Additional Knowledge and Professional Experience
  
  
  
  • Knowledge and experience of programming (with C, C++)
  
  
  • Experience working with Linux operating system
  
  
  
  


• 
  Competences
  
  
  
  • Good English Communication skills (written and speaking)
  
  
  • Teamwork and Collaboration
  
  
  • Assertive Comunication
  
  
  • Adaptability
  
  
  • Problem-Solving
  
  
  • Critical Thinking
  
  
  • Time Management
  
  
  • Interpersonal Skills
  
  
  • Attention to Detail